(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form bit line structures for a dynamic random access memory, (DRAM), chip.
(2) Description of Prior Art
The semiconductor industry is continually striving to reduce the cost of semiconductor chips, while still maintaining, or even decreasing, the cost of the specific chip. The use micro-miniaturization, or the ability to fabricate semiconductor devices, with sub-micron features, have allowed chip cost, and chip performance, to be successfully addressed. The use of sub-micron features has resulted in decreases in performance degrading parasitic capacitances, while also allowing a greater number of smaller chips, with device densities comparable to those obtained using larger chips, to be realized from a specific size starting substrate, thus reducing the processing cost for the smaller chip. However the tighter packing densities, used to obtain aggressive DRAM designs, such as 256 Megabytes or greater, can in some areas, negatively influence DRAM performance.
The high density, DRAM cell array, although resulting in decreased parasitic capacitances, in areas of the transfer gate transistor, can however experience degraded DRAM performance as a result of increasing coupling capacitances, in the region in which bit line structures are closely packed. This invention will offer a process for minimizing the coupling capacitance effect for high density DRAM devices. A process is described in which low bit line to bit line coupling capacitance is achieved, via use of thin bit line wiring structures, in the DRAM cell array, thus reducing the vertical capacitor component, between thin bit line structures. However the bit line wiring structures, for the peripheral devices, are fabricated using thicker metal structures, thus maintaining a low resistance bit line structure in the non-array cell regions of the DRAM chip. This process, thin bit line structures for DRAM cell array, and thicker bit line structures for the peripheral DRAM devices, is accomplished using a damascene process, in which the top portion of the damascene hole, is opened to different depths in an insulator layer, to accommodate the different thickness of bit line structures used for the array and peripherals. Hidaka et al, in U.S. Pat. No. 5,550,769, describe a bit line structure for a semiconductor memory device, however that prior art does not offer the process used in this invention, enabling low resistance, thick bit line structures, for DRAM peripheral devices, and thin bit line structures, for DRAM array devices, to be obtained.